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Microchip Technology /ATSAMS70J20B /TC0 /TC_CHANNEL[0] /EMR

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Interpret as EMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EXTERNAL_TIOAx)TRIGSRCA 0 (EXTERNAL_TIOBx)TRIGSRCB 0 (NODIVCLK)NODIVCLK

TRIGSRCA=EXTERNAL_TIOAx, TRIGSRCB=EXTERNAL_TIOBx

Description

Extended Mode Register (channel = 0)

Fields

TRIGSRCA

Trigger Source for Input A

0 (EXTERNAL_TIOAx): The trigger/capture input A is driven by external pin TIOAx

1 (PWMx): The trigger/capture input A is driven internally by PWMx
TRIGSRCB

Trigger Source for Input B

0 (EXTERNAL_TIOBx): The trigger/capture input B is driven by external pin TIOBx

1 (PWMx): For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
NODIVCLK

No Divided Clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data